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USB2513 USB 2.0 High-Speed 3-Port Hub Controller
PRODUCT FEATURES
General Description
The SMSC 3-Port Hub is low power, OEM configurable, MTT (multi transaction translator) hub controller IC with 3 downstream ports for embedded USB solutions. The 3-port hub is fully compliant with the USB 2.0 Specification and will attach to an upstream port as a Full-Speed Hub or as a Full-/High-Speed Hub. The 3Port Hub supports Low-Speed, Full-Speed, and HighSpeed (if operating as a High-Speed Hub) downstream devices on all of the enabled downstream ports.
Datasheet Flexible port mapping and disable sequence. Ports can be disabled/reordered in any order to support multiple product SKUs. Hub will automatically reorder the remaining ports to match the Host controller's numbering scheme Programmable USB differential-pair pin location Ease PCB layout by aligning USB signal lines directly to connectors Programmable USB signal drive strength. Recover USB signal integrity due to compromised system environment using 3-level driving strength resolution Select the presence of a permanently hardwired USB peripheral device on a port by port basis Configure the delay time for filtering the over-current sense inputs Configure the delay time for turning on downstream port power Configure the polarity of downstream port power control signals Indicate the maximum current that the 3-port hub consumes from the USB upstream port Indicate the maximum current required for the hub controller Supports Custom String Descriptor up to 31 characters in length for:
- Product String - Manufacturer String - Serial Number String
General Features
Hub Controller IC with 3 downstream ports High-performance multiple transaction translator MultiTRAKTM Technology Provides one transaction translator per port Enhanced OEM configuration options available through either a single serial i2C EEPROM, or SMBus Slave Port 36-pin (6x6mm) and 48-Pin (7x7mm) QFN lead-free, RoHS compliant packages Footprint compatible with USB2514 and USB2512 (36-pin QFN) to provide designers with flexibility regarding the quantity of USB expansion ports utilized without redesign
Hardware Features
Low power operation Full Power Management with individual or ganged power control of each downstream port On-chip Power On Reset (POR) Internal 1.8V Voltage Regulator Fully integrated USB termination and Pull-up/Pulldown resistors On Board 24MHz Crystal Driver, Resonator or External 24/48MHz clock input USB host/device speed indicator. Per-port 3-color LED drivers that indicate the speed of USB host and device connection - hi-speed (480 Mbps), full-speed (12 Mbps), low-speed (1.5 Mbps) (48-pin QFN) Enhanced EMI rejection and ESD protection performance
Pin Selectable Options for Default Configuration
-- Select Downstream Ports as Non-Removable Ports -- Select Downstream Ports as Disabled Ports -- Select Downstream Port Power Control and OverCurrent Detection on a Ganged or Individual Basis -- Select Downstream Port Power Control Polarity -- Select USB Signal Drive Strength -- Select USB Differential Pair Pin location -- Select on-chip or off-chip voltage regulator mode
Applications
LCD monitors and TVs Multi-function USB peripherals PC mother boards Set-top boxes, DVD players, DVR/PVR Printers and scanners PC media drive bay Portable hub boxes Mobile PC docking Embedded systems
OEM Selectable Features
Customize Vendor ID, Product ID, and Device ID Select whether the hub is part of a compound device (When any downstream port is permanently hardwired to a USB peripheral device, the hub is part of a compound device)
SMSC USB2513
DATASHEET
Revision 1.98 (11-19-07)
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
ORDER NUMBERS:
USB2513-AEZG FOR 36 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE USB2513-HZH FOR 48 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Table of Contents
Chapter 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 PIN Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 4 Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 3-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Hub Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 VBus Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 QFN and 48 QFN Feature Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Internal Register Set (Common to EEPROM and SMBus) . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 In-Circuit EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Invalid Protocol Response Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 General Call Address Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 Slave Device Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.5 Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.6 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.7 Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.8 SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Configuration Option: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Strapping Options: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Internal POR Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 External Hardware RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.3 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 18 19 19 33 33 34 34 35 35 35 35 35 36 36 36 36 37 37 37 40
4.2 4.3
4.4
4.5 4.6 4.7
Chapter 5 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 5.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 6 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.1 Oscillator/Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 SMBus Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 USB 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 46 46
Chapter 7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SMSC USB2513
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
List of Figures
Figure 1.1 Figure 1.2 Figure 2.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 6.1 Figure 6.2 Figure 7.1 Figure 7.2 USB2513 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 USB2513 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 USB2513 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LED Strapping Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Reset_N Timing for Default/Strap Option Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Formula to find value of C1 and C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 36-Pin QFN, 6x6mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 48-Pin QFN, 7x7mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
List of Tables
Table 3.1 Table 3.2 Table 3.3 Table 3.4 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7 Table 5.1 Table 5.2 USB2514 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SMBus or EEPROM Interface Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 USB2514 Power, Ground, No Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 USB2514 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 36 QFN and 48 QFN Feature Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Internal Default, EEPROM and SMBus Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . 19 Port Remap Register for Ports 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Port Remap Register for Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset_N Timing for Default/Strap Option Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Chapter 1 Pin Configuration
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
VBUS_DET
RESET_N
27
26
25
24
23
22
21
20
SUSP_IND/LOCAL_PWR/NON_REM0 VDDA33 USBUP_DM USBUP_DP XTAL2 XTAL1/CLKIN VDD18PLL RBIAS VDD33PLL
28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 Thermal Slug (must be connected to VSS)
19 18 17 16
OCS3_N
VDD33
NC
NC
PRTPWR3 OCS2_N PRTPWR2 VDD33CR VDD18 OCS1_N PRTPWR1 TEST VDDA33
SMSC USB2513 (Top View QFN-36)
15 14 13 12 11 10
VDDA33
USBDN3_DM/PRT_DOS_M3
USBDN1_DP/PRT_DIS_P1
USBDN2_DP/PRT_DIS_P2
USBDN1_DM/PRT_DIS_M1
USBDN2_DM/PRT_DIS_M2
USBDN3_DP/PRT_DIS_P3
NC
Indicates pins on the bottom of the device.
Figure 1.1 USB2513 36-Pin QFN
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
36
35
34
33
32
31
30
29
28
27
26
LED_A1_N/PRT_SWP1 PRTPWR_POL SUSP_IND/LOCAL_PWR/NON_REM0 SEL48 VDDA33 USBUP_DM USBUP_DP XTAL2 XTAL1/CLKIN VDD18PLL RBIAS VDD33PLL
37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9 Thermal Slug (must be connected to VSS)
25 24 23 22 21
LED_A2_N/PRT_SWP2
LED_B1_N/BOOST0
HS_IND/CFG_SEL1
VBUS_DET
CFG_SEL2
RESET_N
OCS3_N
VDD33
NC
NC
LED_B2_N/BOOST1 LED_A3_N/PRT_SWP3 LED_B3_N/GANG_EN PRTPWR3 OCS2_N PRTPWR2 VDD33CR VDD18 OCS1_N PRTPWR1 TEST NC
SMSC USB2513 (Top View QFN-48)
20 19 18 17 16 15 14 13
REG_EN
NC
NC
VDDA33
USBDN1_DM/PRT_DIS_M1
USBDN2_DM/PRT_DIS_M2
USBDN3_DM/PRT_DIS_M3
USBDN1_DP/PRT_DIS_P1
USBDN2_DP/PRT_DIS_P2
Indicates pins on the bottom of the device.
Figure 1.2 USB2513 48-Pin QFN
SMSC USB2513
7
USBDN3_DP/PRT_DIS_P3
VDDA33
NC
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Chapter 2 Block Diagram
To Upstream VBUS
Upstream USB Data 3.3V
24 MHz Crystal
To EEPROM or SMBus Master 1.8V SD SCK
PLL Bus-Power Detect/VBUS Pulse Upstream PHY 1.8V Reg
Serial Interface
Repeater
SIE
Controller
TT #1
TT #2
TT #3
Port Controller
Routing & Port Re-Ordering Logic
Port #1 PHY#1
OC Sense Switch Driver LED Drivers
Port #2 PHY#2
OC Sense Switch Driver LED Drivers
Port #3 PHY#3
OC Sense Switch Driver LED Drivers
USB Data OC Sense Downstream Switch/LED Drivers
USB Data OC Sense Downstream Switch/LED Drivers
USB Data OC Sense Downstream Switch/LED Drivers
Figure 2.1 USB2513 Block Diagram
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USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Chapter 3 Pin Descriptions
3.1 PIN Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "N" symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. When "N" is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive. Table 3.1 USB2514 Pin Descriptions BUFFER TYPE
SYMBOL
36 QFN
48 QFN
DESCRIPTION
UPSTREAM USB INTERFACES USBUP_DP USBUP_DM 31 30 43 42 IO-U USB Bus Data These pins connect to the upstream USB bus data signals (Host port, or upstream hub). I/O12 Detect Upstream VBUS Power Detects state of Upstream VBUS power. The SMSC Hub monitors VBUS_DET to determine when to assert the internal D+ pull-up resistor (signaling a connect event). When designing a detachable hub, this pin must be connected to the VBUS power pin of the USB port that is upstream of the hub. For self-powered applications with a permanently attached host, this pin must be connected to 3.3V (typically VDD33). DOWNSTREAM 3-PORT USB 2.0 INTERFACE USBDN_DP[3:1]/ PRT_DIS_P[3:1] & USBDN_DM[3:1]/ PRT_DIS_M[3:1] 6 3 1 6 3 1 7 4 2 7 4 2 IO-U High-Speed USB Data & Port Disable Strap Option These pins connect to the downstream USB peripheral devices attached to the hub's port. Downstream Port Disable Strap option: If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled at RESET_N negation to determine if the port is disabled. Both USB data pins for the corresponding port must be tied to the VDDA33 to disable the associated downstream port. PRTPWR[3:1] 18 16 12 21 19 15 O12 USB Power Enable Enables power to USB peripheral devices downstream. The active signal level of the PRTPWR[3:1] pins is determined by the Power Polarity Strapping function of the PRTPWR_POL pin.
VBUS_DET
27
35
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USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Table 3.1 USB2514 Pin Descriptions (continued) BUFFER TYPE I/O12
SYMBOL LED_A[3:1]_N/ PRT_SWP[3:1]
36 QFN n/a
48 QFN 23 25 37
DESCRIPTION Port LED Indicators & Port Swap strapping option Indicator LED for ports 1-3. Will be active low when LED support is enabled via EEPROM or SMBus. If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled at RESET_N negation to determine the electrical connection polarity of the downstream USB Port pins (USB_DP and USB_DM). Also, the active state of the LED will be determined as follows: `0' = Port Polarity is normal, and the LED is active high. `1' = Port Polarity (for USB_DP and USB_DM) is swapped, and the LED is active low.
LED_B3_N/ GANG_EN
n/a
22
I/O12
Enhanced Port 3 LED & Gang Power and Overcurrent Strap Option Enhanced Indicator LED for port 3. Will be active low when LED support is enabled via EEPROM or SMBus. GANG_EN: Selects between Gang or Individual Port power and Over Current sensing. If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled at RESET_N negation to determine the mode as follows: `0' = Individual sensing & switching, and LED_B3_N is active high. `1' = Ganged sensing & switching, and LED_B3_N is active low.
LED_B[2:1]_N/ BOOST[1:0]
n/a
24 36
I/O12
Enhanced Port [2:1] LED & Phy Boost strapping option Enhanced Indicator LED for ports 1 & 2. Will be active low when LED support is enabled via EEPROM or SMBus.
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USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Table 3.1 USB2514 Pin Descriptions (continued) BUFFER TYPE
SYMBOL
36 QFN
48 QFN
DESCRIPTION BOOST[1:0], If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled at RESET_N negation to determine if all PHY ports (upstream and downstream) operate at a normal or boosted electrical level. Also, the active state of the LEDs will be determined as follows: See for BOOST values: Section 4.3.1.26, "Register F6h: Boost_Up" and Section 4.3.1.27, "Register F8h: Boost_3:0". BOOST[1:0] = BOOST_IOUT[1:0] BOOST[1:0] = `00', LED_B2_N is active high, LED_B1_N is active high. BOOST[1:0] = `01', LED_B2_N is active high, LED_B1_N is active low. BOOST[1:0] = `10', LED_B2_N is active low, LED_B1_N is active high. BOOST[1:0] = `11', LED_B2_N is active low, LED_B1_N is active low.
PRTPWR_POL
n/a
38
IPU
Port Power Polarity strapping Port Power Polarity strapping determination for the active signal polarity of the [3:1]PRTPWR pins. While RESET_N is asserted, the logic state of this pin will (through the use of internal combinatorial logic) determine the active state of the [3:1]PRTPWR pins in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. When RESET_N is negated, the logic value will be latched internally, and will retain the active signal polarity for the PRTPWR[3:1] pins. `1' = PRTPWR[3:1]_P/N pins have an active `high' polarity `0' = PRTPWR[3:1]_P/N pins have an active `low' polarity Warning: Active Low port power controllers may glitch the downstream port power when system power is first applied. Care should be taken when designing with active low components! Note: If PRTPWR_POL is not an available pin on the package, the hub will support active high power controllers only!
OCS[3:1]_N
19 17 13
26 20 16
IPU
Over Current Sense Input from external current monitor indicating an overcurrent condition. {Note: Contains internal pull-up to 3.3V supply}
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Table 3.1 USB2514 Pin Descriptions (continued) BUFFER TYPE I-R
SYMBOL RBIAS
36 QFN 35
48 QFN 47
DESCRIPTION USB Transceiver Bias A 12.0k (+/- 1%) resistor is attached from ground to this pin to set the transceiver's internal bias settings.
SERIAL PORT INTERFACE SDA/ SMBDATA/ NON_REM1 22 29 I/OSD12 Serial Data / SMB Data & Port Non Removable Strap Option NON_REM1: Non removable port strap option. If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled (in conjunction with LOCAL_PWR/SUSP_IND/NON_REM0) at RESET_N negation to determine if imports [3:1] contain permanently attached (non-removable) devices: NON_REM[1:0] = `00', All ports are removable, NON_REM[1:0] = `01', Port 1 is nonremovable, NON_REM[1:0] = `10', Ports 1 & 2 are non-removable, NON_REM[1:0] = `11', Ports 1, 2 & 3 are non-removable SCL/ SMBCLK/ CFG_SEL0 24 31 I/OSD12 Serial Clock (SCL) SMBus Clock (SMBCLK) Configuration Select_SEL0: The logic state of this multifunction pin is internally latched on the rising edge of RESET_N (RESET_N negation), and will determine the hub configuration method as described in Table 3.2, "SMBus or EEPROM Interface Behavior". 25 32 I/O12 High-Speed Upstream port indictor & Configuration Programming Select HS_IND: High Speed Indicator for upstream port connection speed. The active state of the LED will be determined as follows: CFG_SEL1 = `0', HS_IND is active high, CFG_SEL1 = `1', HS_IND is active low, `Asserted' = Hub is connected at HS `Negated' = Hub is connected at FS CFG_SEL1: The logic state of this pin is internally latched on the rising edge of RESET_N (RESET_N negation), and will determine the hub configuration method as described in Table 3.2, "SMBus or EEPROM Interface Behavior".
HS_IND/ CFG_SEL1
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Table 3.1 USB2514 Pin Descriptions (continued) BUFFER TYPE I
SYMBOL CFG_SEL2
36 QFN n/a
48 QFN 33
DESCRIPTION Configuration Programming Select Note: This pin is not available in all packages; it is held to a logic `0' when not available The logic state of this pin is internally latched on the rising edge of RESET_N (RESET_N negation), and will determine the hub configuration method as described in Table 3.2, "SMBus or EEPROM Interface Behavior"
MISC XTAL1/ CLKIN 33 45 ICLKx Crystal Input/External Clock Input 24MHz crystal or external clock input. This pin connects to either one terminal of the crystal or to an external 24/48MHz clock when a crystal is not used. Note: XTAL2 32 44 OCLKx 48MHz only available in 48 QFN.
Crystal Output 24MHz Crystal This is the other terminal of the crystal, or pulled high when an external clock source is used to drive XTAL1/CLKIN. This output must not be used to drive any external circuitry other than the crystal circuit.
RESET_N
26
34
IS
RESET Input The system can reset the chip by driving this input low. The minimum active low pulse is 1 us. When the RESET_N pin is pulled to VDD33, the internal POR (Power on Reset) is enabled and no external reset circuitry is required. The internal POR holds the internal logic in reset until the power supplies are stable.
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Table 3.1 USB2514 Pin Descriptions (continued) BUFFER TYPE I/O
SYMBOL SUSP_IND/ LOCAL_PWR/ NON_REM0
36 QFN 28
48 QFN 39
DESCRIPTION Active/Suspend status LED or Local-Power & Non Removable Strap Option Suspend Indicator: Indicates USB state of the hub. `negated' = Unconfigured, or configured and in USB Suspend `asserted' = Hub is configured, and is active (i.e., not in suspend) Local Power: Detects availability of local self-power source. Low = Self/local power source is NOT available (i.e., Hub gets all power from Upstream USB VBus). High = Self/local power source is available. NON_REM0 Strap Option: If this strap is enabled by package and configuration settings (see Table 3.2), this pin will be sampled (in conjunction with NON_REM1) at RESET_N negation to determine if ports [3:1] contain permanently attached (non-removable) devices. Also, the active state of the LED will be determined as follows: NON_REM[1:0] = `00', All ports are removable, and the LED is active high NON_REM[1:0] = `01', Port 1 is nonremovable, and the LED is active low NON_REM[1:0] = `10', Ports 1 & 2 are non-removable, and the LED is active high NON_REM[1:0] = `11', Ports 1, 2 & 3 are nonremovable, and the LED is active low
TEST
11
14
IPD
TEST pin XNOR continuity tests all signal pins on the hub, please contact your SMSC representative for a detailed description of how this test mode is enabled and utilized.
SEL48
n/a
40
I
Select 48 MHz clock input 48MHz external clock input select. When the hub is clocked from an external clock source, this pin selects either 24MHz or 48MHz mode. `0' = 24MHz `1' = 48MHz
REG_EN
n/a
11
IPU
Regulator Enable REG_EN: This pin is internally pulled up to enable the internal 1.8V regulators, and this pin should be treated as a no-connect. In order to disable the regulators, this pin will need to be externally connected to ground. When the internal regulator is enabled, the 1.8V power pins must be left unconnected, except for the required bypass capacitors.
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Table 3.2 SMBus or EEPROM Interface Behavior CFG_SEL2 36-Pin QFN 48-Pin QFN 36-Pin QFN 48-Pin QFN 36-Pin QFN 48-Pin QFN 36-Pin QFN 48-Pin QFN 48-Pin QFN N/A 0 N/A 0 CFG_SEL1 0 0 0 0 CFG_SEL0 0 0 1 1 SMBUS OR EEPROM INTERFACE BEHAVIOR Internal Default Configuration Strap Options Enabled Port Indicators Not Supported
Configured as an SMBus slave for external download of user-defined descriptors. SMBus slave address 58 (0101100x) Strap Options Disabled All Settings Controlled by Registers Internal Default Configuration Strap Options Enabled Bus Power Operation LED Mode = USB 2-Wire I2C EEPROMS are supported. Strap Options Disabled All Settings Controlled by Registers
N/A 0 N/A 0 1
1 1 1 1 0
0 0 1 1 0
Internal Default Configuration Strap Options Disabled Dynamic Power Switching Enabled Internal Default Configuration Strap Options Disabled Dynamic Power Switching Enabled LED Mode = USB Internal Default Configuration Strap Options Disabled Internal Default Configuration Strap Options Disabled LED Mode = USB Ganged Power Switching Ganged Over-Current Sensing
48-Pin QFN
1
0
1
48-Pin QFN 48-Pin QFN
1 1
1 1
0 1
Notes:
Denotes 48-Pin QFN
Denotes 36-Pin QFN
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Table 3.3 USB2514 Power, Ground, No Connect PACKAGE SYMBOL VDD18 36 QFN 14 48 QFN 17 VDD Core +1.8V core power. If the internal regulator is enabled, then this pin must have a 1.0F (or greater) 20% (ESR <0.1) capacitor to VSS. VDD33PLL 36 48 VDD 3.3 PLL Regulator Reference +3.3V power supply for the PLL. If the internal PLL 1.8V regulator is enabled, then this pin acts as the regulator input. VDDPLL18 34 46 VDD PLL +1.8V Filtered analog power for internal PLL. If the internal regulator is enabled, then this pin must have a 1.0F (or greater) 20% (ESR <0.1) capacitor to VSS. VDDA33 5 10 29 23 15 5 10 41 30 18 VDD Analog I/O +3.3V Filtered analog PHY power, shared between adjacent ports. VDDIO/VDD 3.3 Core Regulator Reference +3.3V power supply for the Digital I/O If the internal core regulator is enabled, then VDD33CR acts as the regulator input. VSS Ground FUNCTION
VDD33/VDD33CR
VSS
n/a
n/a
3.2
Buffer Type Descriptions
Table 3.4 USB2514 Buffer Type Descriptions BUFFER I IPD IPU IS O12 OD12 I/O12 Input. Input with internal weak pull-down resistor. Input with internal weak pull-up resistor. Input with Schmitt trigger. Output 12mA. Open drain... 12mA sink. Input/Output buffer with 12mA sink and 12mA source. DESCRIPTION
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Table 3.4 USB2514 Buffer Type Descriptions (continued) BUFFER I/OSD12 DESCRIPTION Open drain...12mA sink with Schmitt trigger, and must meet I2C-Bus Specification Version 2.1 requirements. XTAL clock input. XTAL clock output. RBIAS. Analog Input/Output Defined in USB specification. Analog Input/Output.
ICLKx OCLKx I-R I/O-U AIO
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Chapter 4 Configuration Options
4.1 3-Port Hub
SMSC's USB 2.0 3-Port Hub is fully specification compliant to the Universal Serial Bus Specification Revision 2.0 April 27, 2000 (12/7/2000 and 5/28/2002 Errata). Please reference Chapter 10 (Hub Specification) for general details regarding Hub operation and functionality. For performance reasons, the 3-Port Hub provides 1 Transaction Translator (TT) per port (defined as Multi-TT configuration), divided into 4 non-periodic buffers per TT.
4.1.1
Hub Configuration Options
The SMSC Hub supports a large number of features (some are mutually exclusive), and must be configured in order to correctly function when attached to a USB host controller. There are three principal ways to configure the hub: SMBus, EEPROM, or by internal default settings (with or without pin strapping option over-rides). In all cases, the configuration method will be determined by the CFG_SEL2, CFG_SEL1 and CFG_SEL0 pins immediately after RESET_N negation.
4.1.1.1
Power Switching Polarity
The selection of active state "polarity" for the PRTPWR pins is made by a strapping option only (the PRTPWR_POL pin). Note: If PRTPWR_POL is not an available pin on the package, the hub will support active high power controllers only!
4.1.2
VBus Detect
According to Section 7.2.1 of the USB 2.0 Specification, a downstream port can never provide power to its D+ or D- pull-up resistors unless the upstream port's VBUS is in the asserted (powered) state. The VBUS_DET pin on the Hub monitors the state of the upstream VBUS signal and will not pull-up the D+ resistor if VBUS is not active. If VBUS goes from an active to an inactive state (Not Powered), Hub will remove power from the D+ pull-up resistor within 10 seconds.
4.2
36 QFN and 48 QFN Feature Differences
Table 4.1 36 QFN and 48 QFN Feature Differences
36 QFN N/A N/A N/A N/A Available Available
48 QFN Available Available Available Available N/A N/A 48MHz clock input mode External 1.8V regulators Port LED Indicators Port Swap Strapping Options
FEATURE
Only Active High Port Power Control is supported in 36 QFN package Boost Default Level is used; see Table 4.2, "Internal Default, EEPROM and SMBus Register Memory Map"
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4.3
EEPROM Interface
The SMSC Hub can be configured via a 2-wire (I2C) EEPROM (256x8). (Please see Table 3.1 for specific details on how to enable configuration via an I2C EEPROM). The Internal state-machine will (when configured for EEPROM support) read the external EEPROM for configuration data. The hub will then "attach" to the upstream USB host. Note: The Hub does not have the capacity to write, or "Program," an external EEPROM. The Hub only has the capability to read external EEPROMs. The external eeprom will be read (even if it is blank or non-populated), and the hub will be "configured" with the values that are read. Please see Internal Register Set (Common to EEPROM and SMBus) for a list of data fields available.
4.3.1
Internal Register Set (Common to EEPROM and SMBus)
Table 4.2 Internal Default, EEPROM and SMBus Register Memory Map SMBUS AND EEPROM POR VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
REG ADDR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME VID LSB VID MSB PID LSB PID MSB DID LSB DID MSB Config Data Byte 1 Config Data Byte 2 Config Data Byte 3 Non-Removable Devices Port Disable (Self) Port Disable (Bus) Max Power (Self) Max Power (Bus) Hub Controller Max Current (Self) Hub Controller Max Current (Bus) Power-on Time LANG_ID_H LANG_ID_L MFR_STR_LEN PRD_STR_LEN
ABBR VIDL VIDM PIDL PIDM DIDL DIDM CFG1 CFG2 CFG3 NRD PDS PDB MAXPS MAXPB HCMCS HCMCB PWRT LANGIDH LANGIDL MFRSL PRDSL
INTERNAL DEFAULT ROM 24h 04h 13h 25h 00h 00h 9Bh 10h 00h 00h 00h 00h 01h 64h 01h 64h 32h 00h 00h 00h 00h
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Table 4.2 Internal Default, EEPROM and SMBus Register Memory Map (continued) SMBUS AND EEPROM POR VALUES 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
REG ADDR 15h 16h-53h 54h-91h 92h-Cfh D0h-F5h F6h F7h F8h F9h FAh FBh FCh FDh-FEh FFh
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME SER_STR_LEN MFR_STR PROD_STR SER_STR Reserved Boost_Up Reserved Boost_3:0 Reserved Port Swap Port Remap 12 Port Remap 3 Reserved Status/Command Note: SMBus register only
ABBR SERSL MANSTR PRDSTR SERSTR N/A BOOSTUP N/A BOOST30 N/A PRTSP PRTR12 PRTR3 N/A STCD
INTERNAL DEFAULT ROM 00h 00h 00h 00h 01h 00h 00h 00h 00h 00h 00h 00h 00h 00h
4.3.1.1
BIT NUMBER 7:0
Register 00h: Vendor ID (LSB)
BIT NAME VID_LSB
DESCRIPTION Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). This field is set by the OEM using either the SMBus or EEPROM interface options.
4.3.1.2
BIT NUMBER 7:0
Register 01h: Vendor ID (MSB)
BIT NAME VID_MSB
DESCRIPTION Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). This field is set by the OEM using either the SMBus or EEPROM interface options.
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4.3.1.3
BIT NUMBER 7:0
Register 02h: Product ID (LSB)
BIT NAME PID_LSB
DESCRIPTION Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options.
4.3.1.4
BIT NUMBER 7:0
Register 03h: Product ID (MSB)
BIT NAME PID_MSB
DESCRIPTION Most Significant Byte of the Product ID. This is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options.
4.3.1.5
BIT NUMBER 7:0
Register 04h: Device ID (LSB)
BIT NAME DID_LSB
DESCRIPTION Least Significant Byte of the Device ID. This is a 16-bit device release number in BCD format (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options.
4.3.1.6
BIT NUMBER 7:0
Register 05h: Device ID (MSB)
BIT NAME DID_MSB
DESCRIPTION Most Significant Byte of the Device ID. This is a 16-bit device release number in BCD format (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options.
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4.3.1.7
BIT NUMBER 7
Register 06h: CONFIG_BYTE_1
BIT NAME SELF_BUS_PWR
DESCRIPTION Self or Bus Power: Selects between Self- and Bus-Powered operation. The Hub is either Self-Powered (draws less than 2mA of upstream bus power) or Bus-Powered (limited to a 100mA maximum of upstream power prior to being configured by the host controller). When configured as a Bus-Powered device, the SMSC Hub consumes less than 100mA of current prior to being configured. After configuration, the BusPowered SMSC Hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100mA per externally available downstream port) must consume no more than 500mA of upstream VBUS current. The current consumption is system dependent, and the OEM must ensure that the USB 2.0 specifications are not violated. When configured as a Self-Powered device, <1mA of upstream VBUS current is consumed and all ports are available, with each port being capable of sourcing 500mA of current. This field is set by the OEM using either the SMBus or EEPROM interface options. Please see the description under Dynamic Power for the self/bus power functionality when dynamic power switching is enabled. 0 = Bus-Powered operation 1 = Self-Powered operation Note: If Dynamic Power Switching is enabled, this bit is ignored and the LOCAL_PWR pin is used to determine if the hub is operating from self or bus power.
6 5
Reserved HS_DISABLE
Reserved High Speed Disable: Disables the capability to attach as either a High/Fullspeed device, and forces attachment as Full-speed only (i.e. no High-Speed support). 0 = High-/Full-Speed 1 = Full-Speed-Only (High-Speed disabled!)
4
MTT_ENABLE
Multi-TT enable: Enables one transaction translator per port operation. Selects between a mode where only one transaction translator is available for all ports (Single-TT), or each port gets a dedicated transaction translator (Multi-TT) {Note: The host may force Single-TT mode only}. 0 = single TT for all ports 1 = one TT per port (multiple TT's supported)
3
EOP_DISABLE
EOP Disable: Disables EOP generation of EOF1 when in Full-Speed mode. During FS operation only, this permits the Hub to send EOP if no downstream traffic is detected at EOF1. See Section 11.3.1 of the USB 2.0 Specification for additional details. Note: generation of an EOP at the EOF1 point may prevent a Host controller (operating in FS mode) from placing the USB bus in suspend. 0 = EOP generation is normal 1 = EOP generation is disabled
2:1
CURRENT_SNS
Over Current Sense: Selects current sensing on a port-by-port basis, all ports ganged, or none (only for bus-powered hubs). The ability to support current sensing on a port or ganged basis is hardware implementation dependent. 00 = Ganged sensing (all ports together) 01 = Individual port-by-port 1x = Over current sensing not supported (must only be used with BusPowered configurations!)
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BIT NUMBER 0
BIT NAME PORT_PWR
DESCRIPTION Port Power Switching: Enables power switching on all ports simultaneously (ganged), or port power is individually switched on and off on a port- by-port basis (individual). The ability to support power enabling on a port or ganged basis is hardware implementation dependent. 0 = Ganged switching (all ports together) 1 = Individual port-by-port switching
4.3.1.8
BIT NUMBER 7
Register 07h: Configuration Data Byte 2
BIT NAME DYNAMIC
DESCRIPTION Dynamic Power Enable: Controls the ability of the Hub to automatically change from Self-Powered operation to Bus-Powered operation if the local power source is removed or is unavailable (and from Bus-Powered to SelfPowered if the local power source is restored). {Note: If the local power source is available, the Hub will always switch to Self-Powered operation.} When Dynamic Power switching is enabled, the Hub detects the availability of a local power source by monitoring the external LOCAL_PWR pin. If the Hub detects a change in power source availability, the Hub immediately disconnects and removes power from all downstream devices and disconnects the upstream port. The Hub will then re-attach to the upstream port as either a Bus-Powered Hub (if local-power is unavailable) or a SelfPowered Hub (if local power is available). 0 = No Dynamic auto-switching 1 = Dynamic Auto-switching capable
6 5:4
Reserved OC_TIMER
Reserved OverCurrent Timer: Over Current Timer delay. 00 = 0.1ms 01 = 4ms 10 = 8ms 11 = 16ms
3
COMPOUND
Compound Device: Allows the OEM to indicate that the Hub is part of a compound (see the USB Specification for definition) device. The applicable port(s) must also be defined as having a "Non-Removable Device".
Note: When configured via strapping options, declaring a port as nonremovable automatically causes the hub controller to report that it is part of a compound device.
0 = No 1 = Yes, Hub is part of a compound device
2:0 Reserved Reserved
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4.3.1.9
BIT NUMBER 7:4 3
Register 08h: Configuration Data Byte 3
BIT NAME Reserved PRTMAP_EN Reserved
DESCRIPTION
Port Re-mapping enable: Selects the method used by the hub to assign port numbers and disable ports. `0' = Standard Mode `1' = Port Re-map mode
2:1
LED_MODE
LED Mode Selection: The LED_A[4:1]_N and LED_B[4:1]_N pins support several different modes of operation. `00' = USB Mode `01' = Speed Indication Mode `10' = Same as `00', USB Mode `11' = Same as `00', USB Mode Warning: Do not enable an LED mode that requires LED pins that are not available in the specific package being used in the implementation! Note: The Hub will only report that it supports LED's to the host when USB mode is selected. All other modes will be reported as No LED Support.
0
STRING_EN
Enables String Descriptor Support `0' = String Support Disabled `1' = String Support Enabled
4.3.1.10
BIT NUMBER 7:0
Register 09h: Non-Removable Device
BIT NAME NR_DEVICE
DESCRIPTION Non-Removable Device: Indicates which port(s) include non-removable devices. `0' = port is removable, `1' = port is non-removable. Informs the Host if one of the active ports has a permanent device that is undetachable from the Hub. (Note: The device must provide its own descriptor data.) When using the internal default option, the NON_REM[1:0] pins will designate the appropriate ports as being non- removable. Bit Bit Bit Bit Bit Bit Bit Bit 7= Reserved 6= Reserved 5= Reserved 4= Reserved 3= 1; Port 3 non-removable 2= 1; Port 2 non-removable 1= 1; Port 1 non removable 0 is Reserved, always = `0'
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4.3.1.11
BIT NUMBER 7:0
Register 0Ah: Port Disable For Self Powered Operation
BIT NAME PORT_DIS_SP
DESCRIPTION Port Disable Self-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. During Self-Powered operation when remapping mode is disabled (PRTMAP_EN='0'), this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a Host Controller. The ports can be disabled in any order, the internal logic will automatically report the correct number of enabled ports to the USB Host, and will reorder the active ports in order to ensure proper function. Bit Bit Bit Bit Bit Bit Bit Bit 7= Reserved 6= Reserved 5= Reserved 4= Reserved 3= 1; Port 3 is 2= 1; Port 2 is 1= 1; Port 1 is 0 is Reserved,
disabled disabled disabled always = `0'
4.3.1.12
BIT NUMBER 7:0
Register 0Bh: Port Disable For Bus Powered Operation
BIT NAME PORT_DIS_BP
DESCRIPTION Port Disable Bus-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. During Self-Powered operation when remapping mode is disabled (PRTMAP_EN='0'), this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a Host Controller. The ports can be disabled in any order, the internal logic will automatically report the correct number of enabled ports to the USB Host, and will reorder the active ports in order to ensure proper function. When using the internal default option, the PRT_DIS[1:0] pins will disable the appropriate ports. Bit Bit Bit Bit Bit Bit Bit Bit 7= Reserved 6= Reserved 5= Reserved 4= Reserved 3= 1; Port 3 is 2= 1; Port 2 is 1= 1; Port 1 is 0 is Reserved,
disabled disabled disabled always = `0'
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4.3.1.13
BIT NUMBER 7:0
Register 0Ch: Max Power For Self Powered Operation
BIT NAME MAX_PWR_SP
DESCRIPTION Max Power Self_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. Note: The USB 2.0 Specification does not permit this value to exceed 100mA
4.3.1.14
BIT NUMBER 7:0
Register 0Dh: Max Power For Bus Powered Operation
BIT NAME MAX_PWR_BP
DESCRIPTION Max Power Bus_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a bus-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors.
4.3.1.15
BIT NUMBER 7:0
Register 0Eh: Hub Controller Max Current For Self Powered Operation
BIT NAME HC_MAX_C_SP
DESCRIPTION Hub Controller Max Current Self-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Note: The USB 2.0 Specification does not permit this value to exceed 100mA
A value of 50 (decimal) indicates 100mA, which is the default value.
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4.3.1.16
BIT NUMBER 7:0
Register 0Fh: Hub Controller Max Current For Bus Powered Operation
BIT NAME HC_MAX_C_BP
DESCRIPTION Hub Controller Max Current Bus-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a buspowered hub. This value will include the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value will NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. A value of 50 (decimal) would indicate 100mA, which is the default value.
4.3.1.17
BIT NUMBER 7:0
Register 10h: Power-On Time
BIT NAME POWER_ON_TIME
DESCRIPTION Power On Time: The length of time that it takes (in 2 ms intervals) from the time the host initiated power-on sequence begins on a port until power is good on that port.
4.3.1.18
BIT NUMBER 7:0
Register 11h: Language ID High
BIT NAME LANG_ID_H
DESCRIPTION USB LANGUAGE ID (Upper 8 bits of a 16 bit ID field)
4.3.1.19
BIT NUMBER 7:0
Register 12h: Language ID Low
BIT NAME LANG_ID_L
DESCRIPTION USB LANGUAGE ID (Lower 8 bits of a 16 bit ID field)
4.3.1.20
BIT NUMBER 7:0
Register 13h: Manufacturer String Length
BIT NAME MFR_STR_LEN Manufacturer String Length
DESCRIPTION
Maximum string length is 31 characters
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BIT NUMBER 7:0
Register 14h: Product String Length
BIT NAME PRD_STR_LEN Product String Length
DESCRIPTION
Maximum string length is 31 characters
4.3.1.22
BIT NUMBER 7:0
Register 15h: Serial String Length
BIT NAME SER_STR_LEN Serial String Length
DESCRIPTION
Maximum string length is 31 characters
4.3.1.23
BIT NUMBER 7:0
Register 16h-53h: Manufacturer String
BIT NAME MFR_STR
DESCRIPTION Manufacturer String, UNICODE UTF-16LE per USB 2.0 Specification Maximum string length is 31 characters (62 bytes) Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters. The Characters will be stored starting with the LSB at the least significant address and the MSB at the next 8-bit location (subsequent characters must be stored in sequential contiguous address in the same LSB, MSB manner). Some EEPROM programmers may transpose the MSB and LSB, thus reversing the Byte order. Please pay careful attention to the Byte ordering or your selected programming tools.
4.3.1.24
BIT NUMBER 7:0
Register 54h-91h: Product String
BIT NAME PRD_STR
DESCRIPTION Product String, UNICODE UTF-16LE per USB 2.0 Specification Maximum string length is 31 characters (62 bytes) Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters. The Characters will be stored starting with the LSB at the least significant address and the MSB at the next 8-bit location (subsequent characters must be stored in sequential contiguous address in the same LSB, MSB manner). Some EEPROM programmers may transpose the MSB and LSB, thus reversing the Byte order. Please pay careful attention to the Byte ordering or your selected programming tools.
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BIT NUMBER 7:0
Register 92h-CFh: Serial String
BIT NAME SER_STR
DESCRIPTION Serial String, UNICODE UTF16LE per USB 2.0 Specification Maximum string length is 31 characters (62 bytes) Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters. The Characters will be stored starting with the LSB at the least significant address and the MSB at the next 8-bit location (subsequent characters must be stored in sequential contiguous address in the same LSB, MSB manner). Some EEPROM programmers may transpose the MSB and LSB, thus reversing the Byte order. Please pay careful attention to the Byte ordering or your selected programming tools.
4.3.1.26
BIT NUMBER 7:2 1:0
Register F6h: Boost_Up
BIT NAME Reserved BOOST_IOUT Reserved
DESCRIPTION
Upstream USB electrical signaling drive strength Boost Bit for Upstream Port. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB Compliant parameters (one example would be Test J/K levels), the OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signalling levels.
4.3.1.27
BIT NUMBER 7:6 5:4
Register F8h: Boost_3:0
BIT NAME Reserved BOOST_IOUT_3 Note: Reserved
DESCRIPTION
Upstream USB electrical signaling drive strength Boost Bit for Downstream Port `3'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB Compliant parameters (one example would be Test J/K levels), the OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signalling levels.
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BIT NUMBER 3:2
BIT NAME BOOST_IOUT_2
DESCRIPTION Upstream USB electrical signaling drive strength Boost Bit for Downstream Port `2'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB Compliant parameters (one example would be Test J/K levels), the OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signalling levels.
1:0
BOOST_IOUT_1
Upstream USB electrical signaling drive strength Boost Bit for Downstream Port `1'. `00' = Normal electrical drive strength = No boost `01' = Elevated electrical drive strength = Low (approximately 4% boost) `10' = Elevated electrical drive strength = Medium (approximately 8% boost) `11' = Elevated electrical drive strength = High (approximately 12% boost) Note: "Boost" could result in non-USB Compliant parameters (one example would be Test J/K levels), the OEM should use a `00' value unless specific implementation issues require additional signal boosting to correct for degraded USB signalling levels.
4.3.1.28
BIT NUMBER 7:0
Register FAh: Port Swap
BIT NAME PRTSP
DESCRIPTION Port Swap: Swaps the Upstream and Downstream USB DP and DM Pins for ease of board routing to devices and connectors. `0' = USB D+ functionality is associated with the DP pin and D- functionality is associated with the DM pin. `1' = USB D+ functionality is associated with the DM pin and D- functionality is associated with the DP pin. Bit Bit Bit Bit Bit Bit Bit Bit 7= 6= 5= 4= 3= 2= 1= 0= Reserved Reserved Reserved Reserved `1'; Port 3 DP/DM is Swapped. `1'; Port 2 DP/DM is Swapped. `1'; Port 1 DP/DM is Swapped. `1'; Upstream Port DP/DM is Swapped
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BIT NUMBER 7:0
Register FBh: Port Remap 12
BIT NAME PRTR12
DESCRIPTION Port remap register for ports 1 & 2. When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has; the hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number '1', up to the number of ports that the hub reported having. The host's port number is referred to as "Logical Port Number" and the physical port on the hub is the "Physical Port Number". When remapping mode is enabled (see PRTMAP_EN in Register 08h: Configuration Data Byte 3) the hub's downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that Contiguous Logical Port Numbers are used, starting from #1 up to the maximum number of enabled ports; this ensures that the hub's ports are numbered in accordance with the way a Host will communicate with the ports. Table 4.3 Port Remap Register for Ports 1 & 2 Bit [7:4] `0000' `0001' `0010' `0011' `0100' to `1111' Bit [3:0] `0000' `0001' `0010' `0011' `0100' to `1111' Physical Port 2 is Disabled Physical Port 2 is mapped to Logical Port 1 Physical Port 2 is mapped to Logical Port 2 Physical Port 2 is mapped to Logical Port 3 Illegal; Do Not Use
Physical Port 1 is Disabled Physical Port 1 is mapped to Logical Port 1 Physical Port 1 is mapped to Logical Port 2 Physical Port 1 is mapped to Logical Port 3 Illegal; Do Not Use
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BIT NUMBER 7:0
Register FCh: Port Remap 3
BIT NAME PRTR3 Port remap register for port 3.
DESCRIPTION
When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has; the hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number '1', up to the number of ports that the hub reported having. The host's port number is referred to as "Logical Port Number" and the physical port on the hub is the "Physical Port Number". When remapping mode is enabled (see PRTMAP_EN in Register 08h: Configuration Data Byte 3) the hub's downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that Contiguous Logical Port Numbers are used, starting from #1 up to the maximum number of enabled ports; this ensures that the hub's ports are numbered in accordance with the way a Host will communicate with the ports. Table 4.4 Port Remap Register for Port 3 Bit [7:4] `0000' `0001' `0010' `0011' `0100' to `1111' Bit [3:0] `0000' `0001' `0010' `0011' `0100' to `1111' Reserved Reserved Reserved Reserved Illegal; Do Not Use
Physical Port 3 is Disabled Physical Port 3 is mapped to Logical Port 1 Physical Port 3 is mapped to Logical Port 2 Physical Port 3 is mapped to Logical Port 3 Illegal; Do Not Use
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BIT NUMBER 7:3 2
Register FFh: Status/Command
BIT NAME Reserved INTF_PW_DN Reserved
DESCRIPTION
SMBus Interface Power Down `0' = Interface is active `1' = Interface power down after ACK has completed
1
RESET
Reset the SMBus Interface and internal memory back to RESET_N assertion default settings. `0' = Normal Run/Idle State `1' = Force a reset of registers to their default state
0
USB_ATTACH
USB Attach (and write protect) `0' = SMBus slave interface is active `1' = Hub will signal a USB attach event to an upstream device, and the internal memory (address range 00h-FEh) is "write-protected" to prevent unintentional data corruption.
4.3.2
I2C EEPROM
The I2C EEPROM interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The Hub's I2C EEPROM interface is designed to attach to a single "dedicated" I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. Note: Extensions to the I2C Specification are not supported. The Hub acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions.
4.3.2.1
Implementation Characteristics
The Hub will only access an EEPROM using the Sequential Read Protocol.
4.3.2.2
Pull-Up Resistor
The Circuit board designer is required to place external pull-up resistors (10K recommended) on the SDA/SMBDATA & SCL/SMBCLK/CFG_SELO lines (per SMBus 1.0 Specification, and EEPROM manufacturer guidelines) to Vcc in order to assure proper operation.
4.3.2.3
I2C EEPROM Slave Address
Slave address is 1010000. Note: 10-bit addressing is NOT supported.
4.3.3
In-Circuit EEPROM Programming
The EEPROM can be programmed via ATE by pulling RESET_N low (which tri-states the Hub's EEPROM interface and allows an external source to program the EEPROM).
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4.4
SMBus Slave Interface
Instead of loading User-Defined Descriptor data from an external EEPROM, the SMSC Hub can be configured to receive a code load from an external processor via an SMBus interface. The SMBus interface shares the same pins as the EEPROM interface; if CFG_SEL1 & CFG_SEL0 activates the SMBus interface, external EEPROM support is no longer available (and the user-defined descriptor data must be downloaded via the SMBus). Due to system issues, the SMSC Hub waits indefinitely for the SMBus code load to complete and only "appears" as a newly connected device on USB after the code load is complete. The Hub's SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports two protocols. The Write Block and Read Block protocols are the only valid SMBus protocols for the Hub. The Hub responds to other protocols as described in Section 4.4.2, "Invalid Protocol Response Behavior," on page 35. Reference the System Management Bus Specification, Rev 1.0. The SMBus interface is used to read and write the registers in the device. The register set is shown in Section 4.3.1, "Internal Register Set (Common to EEPROM and SMBus)," on page 19.
4.4.1
Bus Protocols
Typical Write Block and Read Block protocols are shown below. Register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates the Hub driving data on the SMBDATA line; otherwise, host data is on the SDA/SMBDATA line. The slave address is the unique SMBus Interface Address for the Hub that identifies it on SMBus. The register address field is the internal address of the register to be accessed. The register data field is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read. Note: Data bytes are transferred MSB first (msb first).
4.4.1.1
Block Read/Write
The Block Write begins with a slave address and a write condition. After the command code, the host issues a byte count which describes how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. Note: For the following SMBus tables:
Denotes Master-to-Slave
Denotes Slave-to-Master
1 S
7 Slave Address
1 Wr
1 A
8 Register Address
1 A ... 8 Data byte N 1 A 1 P
8
Byte Count = N
1 A
8 Data byte 1
1 A
8 Data byte 2 Block Write
1 A
Figure 4.1 Block Write
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Block Read A Block Read differs from a block write in that the repeated start condition exists to satisfy the I2C specification's requirement for a change in the transfer direction.
1 S
7 Slave Address
1 Wr
1 A
8 Register Address
1 A
1 S
7 Slave Address
1 Rd
1 A ... 1 P
8 Byte Count = N
1 A
8 Data byte 1
1 A
8 Data byte 2 Block Read
1 A
8 Data byte N
1 A
Figure 4.2 Block Read
4.4.2
Invalid Protocol Response Behavior
Registers that are accessed with an invalid protocol are not updated. A register is only updated following a valid protocol. The only valid protocols are Write Block and Read Block, which are described above. The Hub only responds to the hardware selected Slave Address. Attempting to communicate with the Hub over SMBus with an invalid slave address or invalid protocol results in no response, and the SMBus Slave Interface returns to the idle state. The only valid registers that are accessible by the SMBus slave address are the registers defined in the Registers Section. See Section 4.4.3 for the response to undefined registers.
4.4.3
General Call Address Response
The Hub does not respond to a general call address of 0000_000b.
4.4.4
Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than 35ms (TTIMEOUT, MAX). Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its communications port after a start or stop condition. The Slave Device Time-Out must be implemented.
4.4.5
Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch the SCLK.
4.4.6
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the "Timing Diagram" section.
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4.4.7
Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed immediately by a STOP field.
4.4.8
SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
4.4.8.1
Undefined Registers
The registers shown in Table 4.2 are the defined registers in the Hub. Reads to undefined registers return 00h. Writes to undefined registers have no effect and do not return an error.
4.4.8.2
Reserved Registers
Unless otherwise instructed, only a `0' may be written to all reserved registers or bits.
4.5
Default Configuration Option:
The SMSC Hub can be configured via its internal default configuration. (please see Section 4.3.1, "Internal Register Set (Common to EEPROM and SMBus)" for specific details on how to enable default configuration.) Please refer to Table 4.2 for the internal default values that are loaded when this option is selected.
4.6
Default Strapping Options:
The USB2514 can be configured via a combination of internal default values and pin strap options. Please see Table 3.1 and Table 3.2 for specific details on how to enable the default/pin-strap configuration option. The strapping option pins only cover a limited sub-set of the configuration options. The internal default values will be used for the bits & registers that are not controlled by a strapping option pin. Please refer to Table 4.2 for the internal default values that are loaded when this option is selected. The Green LED pins are sampled after RESET_N negation, and the logic values are used to configure the hub if the internal default configuration mode is selected. The implementation shown below (see Figure 4.3) shows a recommended passive scheme. When a pin is configured with a "Strap High" configuration, the LED functions with active low signalling, and the PAD will "sink" the current from the external supply. When a pin is configured with a "Strap Low" configuration, the LED functions with active high signalling, and the PAD will "source" the current to the external LED.
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+V Strap High
100K
LED Pin
LED
HUB
LED Pin
100K LED
Strap Low
Figure 4.3 LED Strapping Option
4.7
Reset
There are two different resets that the Hub experiences. One is a hardware reset (either from the internal POR reset circuit or via the RESET_N pin) and the second is a USB Bus Reset.
4.7.1
Internal POR Hardware Reset
All reset timing parameters are guaranteed by design.
4.7.2
External Hardware RESET_N
A valid hardware reset is defined as assertion of RESET_N for a minimum of 1us after all power supplies are within operating range. While reset is asserted, the Hub (and its associated external circuitry) consumes less than 500A of current from the upstream USB power source. Assertion of RESET_N (external pin) causes the following: 1. All downstream ports are disabled, and PRTPWR power to downstream devices is removed. 2. The PHYs are disabled, and the differential pairs will be in a high-impedance state. 3. All transactions immediately terminate; no states are saved. 4. All internal registers return to the default state (in most cases, 00(h)). 5. The external crystal oscillator is halted. 6. The PLL is halted. 7. LED indicators are disabled. The Hub is "operational" 500s after RESET_N is negated. Once operational, the Hub immediately reads OEM-specific data from the external EEPROM (if the SMBus option is not disabled).
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4.7.2.1
RESET_N for Strapping Option Configuration
Drive Strap Outputs to inactive levels Attach USB Upstream Start completion request response
Hardware reset asserted
Read Strap Options
USB Reset recovery
Idle
t1 t2
RESET_N
t5 t3
t6
t7
t8
VSS
t4
Strap Pins Don't Care VSS Valid Don't Care Driven by Hub if strap is an output.
Figure 4.4 Reset_N Timing for Default/Strap Option Mode Table 4.5 Reset_N Timing for Default/Strap Option Mode NAME t1 t2 t3 t4 t5 t6 t7 t8 DESCRIPTION RESET_N Asserted. Strap Setup Time Strap Hold Time. hub outputs driven to inactive logic states USB Attach (See Note). Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage). Notes: When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t1+t5. All Power Supplies must have reached the operating levels mandated in Chapter 5, DC Parameters, prior to (or coincident with) the assertion of RESET_N. 100 undefined 5 MIN 1 16.7 16.7 1.5 1400 2 100 TYP MAX UNITS sec nsec nsec sec msec msec msec msec
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4.7.2.2
RESET_N for EEPROM Configuration
Start completion request response
Hardware reset asserted
Read Strap Options
Read EEPROM + Set Options
Attach USB Upstream
USB Reset recovery
Idle
t4 t1
RESET_N
t2
t3
t5
t6
t7
VSS
Figure 4.5 Reset_N Timing for EEPROM Mode Table 4.6 Reset_N Timing for EEPROM Mode NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION RESET_N Asserted. Hub Recovery/Stabilization. EEPROM Read / Hub Config. USB Attach (See Note). Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage). Notes: When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t4+t5+t6+t7. All Power Supplies must have reached the operating levels mandated in Chapter 5, DC Parameters, prior to (or coincident with) the assertion of RESET_N. 100 undefined 5 2.0 MIN 1 500 99.5 100 TYP MAX UNITS sec sec msec msec msec msec msec
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4.7.2.3
RESET_N for SMBus Slave Configuration
Hardware reset asserted Reset Negation SMBus Code Load Hub PHY Stabilization Attach USB Upstream USB Reset recovery Idle Start completion request response
t1
RESET_N
t2
t3
t4
t5
t6
t7
VSS
Figure 4.6 Reset_N Timing for SMBus Mode Table 4.7 Reset_N Timing for SMBus Mode NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION RESET_N Asserted. Hub Recovery/Stabilization. SMBus Code Load (See Note). Hub Configuration and USB Attach. Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage). Notes: For Bus-Powered configurations, the 99.5ms (MAX) is required, and the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t2+t3+t4+t5+t6+t7. For Self-Powered configurations, t3 MAX is not applicable and the time to load the configuration is determined by the external SMBus host. All Power Supplies must have reached the operating levels mandated in Chapter 5, DC Parameters, prior to (or coincident with) the assertion of RESET_N. 100 Undefined 5 250 MIN 1 500 300 100 TYP MAX UNITS sec sec msec msec msec msec msec
4.7.3
USB Bus Reset
In response to the upstream port signaling a reset to the Hub, the Hub does the following: Note: The Hub does not propagate the upstream USB reset to downstream devices. 1. Sets default address to 0. 2. Sets configuration to: Unconfigured. 3. Negates PRTPWR[3:1] to all downstream ports. 4. Clears all TT buffers.
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5. Moves device from suspended to active (if suspended). 6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence. The Host then configures the Hub and the Hub's downstream port devices in accordance with the USB Specification.
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Chapter 5 DC Parameters
5.1 Maximum Guaranteed Ratings
SYMBOL TA MIN -55 MAX 150 325 VDDA18PLL, VDD18 VDDA33, VDD33PLL, VDD33, VDD33CR -0.5 -0.5 -0.5 2.5 4.6 UNITS C C V V Soldering < 10 seconds COMMENTS
PARAMETER Storage Temperature Lead Temperature 1.8V supply voltage 3.3V supply voltage
Voltage on any I/O pin Voltage on XTAL1 Voltage on XTAL2
5.5 4.0 3.6
V V V
Note: Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
5.2
Recommended Operating Conditions
PARAMETER Operating Temperature SYMBOL TA VDDA18PLL VDD18 VDDA33 VDDA33PLL VDD33 VDD33CR MIN 0 1.62 3.0 MAX 70 1.98 3.6 UNITS C V V COMMENTS
1.8V supply voltage 3.3V supply voltage
Voltage on any I/O pin
-0.3
5.5
V
If any 3.3V supply voltage drops b e l o w 3 . 0 V, t h e n t h e M A X becomes: (3.3V supply voltage) + 0.5
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PARAMETER Voltage on XTAL1 Voltage on XTAL2
SYMBOL
MIN -0.3 -0.3
MAX VDDA33 VDD18
UNITS V V
COMMENTS
Table 5.1 DC Electrical Characteristics PARAMETER I, IS Type Input Buffer Low Input Level High Input Level Input Leakage Hysteresis (`IS' Only) Input Buffer with Pull-Up (IPU) Low Input Level High Input Level Low Input Leakage High Input Leakage Input Buffer with PullDown (IPD) Low Input Level High Input Level Low Input Leakage High Input Leakage ICLK Input Buffer Low Input Level High Input Level Input Leakage VILCK VIHCK IIL 1.4 -10 +10 0.5 V V uA VIN = 0 to VDD33 VILI VIHI IILL IIHL 2.0 +10 -35 -10 -90 0.8 V V uA uA VIN = 0 VIN = VDD33 TTL Levels VILI VIHI IILL IIHL 2.0 +35 -10 +90 +10 0.8 V V uA uA VIN = 0 VIN = VDD33 TTL Levels VILI VIHI IIL VHYSI 2.0 -10 250 +10 350 0.8 V V uA mV VIN = 0 to VDD33 TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS
O12, I/O12 &I/OSD12 Type Buffer Low Output Level High Output Level Output Leakage Hysteresis (`SD' pad only) VOL VOH IOL VHYSC 2.4 -10 250 +10 350 0.4 V V uA mV IOL = 12mA @ VDD33 = 3.3V IOH = -12mA @ VDD33 = 3.3V VIN = 0 to VDD33 (Note 5.1)
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DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller
Datasheet
Table 5.1 DC Electrical Characteristics (continued) PARAMETER IO-U (Note 5.2) Supply Current Unconfigured High-Speed Host Full-Speed Host Supply Current Configured (High-Speed Host) 1 2 2 3 Port HS, 1 Port LS/FS Ports @ LS/FS Ports @ HS Ports @ HS IHCH1C1 IHCC2 IHCH2 IHCH3 150 140 155 160 160 150 250 260 mA mA mA mA All supplies combined ICCINTHS ICCINITFS 95 80 105 90 mA mA All supplies combined SYMBOL MIN TYP MAX UNITS COMMENTS
Supply Current Configured (Full-Speed Host) 1 Port 2 Ports 3 Ports Supply Current Suspend Supply Current Reset Note 5.1 Note 5.2 IFCC1 IFCC2 IFCC3 ICSBY ICRST 125 125 125 310 100 135 135 135 420 230 mA mA mA A A
All supplies combined All supplies combined
Output leakage is measured with the current pins in high impedance. See USB 2.0 Specification for USB DC electrical characteristics.
Revision 1.98 (11-19-07)
44
SMSC USB2513
DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller
Datasheet
CAPACITANCE TA = 25C; fc = 1MHz; VDD18, VDDPLL = 1.8V
Table 5.2 Pin Capacitance LIMITS PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CXTAL CIN COUT MIN TYP MAX 2 10 20 UNIT pF pF pF TEST CONDITION All pins except USB pins (and pins under test tied to AC ground)
SMSC USB2513
45
Revision 1.98 (11-19-07)
DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller
Datasheet
Chapter 6 AC Specifications
6.1 Oscillator/Clock
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz 350ppm. External Clock: 50% Duty cycle 10%, 24/48 MHz 350ppm, Jitter < 100ps rms.
XTAL1 (C S 1 = C B + C XTAL ) C1
C ry s ta l
CL
1M eg
C2
XTAL2 (C S 2 = C B + C XTAL )
Figure 6.1 Typical Crystal Circuit Note: CB equals total board/trace capacitance.
(C1 + CS1) x (C2 + CS2) = CL (C1 + CS1 + C2 + CS2)
Figure 6.2 Formula to find value of C1 and C2
6.1.1
SMBus Interface:
The SMSC Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the SMBus 1.0 Specification for Slave-Only devices (except as noted in Section 4.4, "SMBus Slave Interface").
6.1.2
I2C EEPROM:
Frequency is fixed at 58.6KHz 20%.
6.1.3
USB 2.0
The SMSC Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 Specification. Please refer to the USB 2.0 Specification for more information.
Revision 1.98 (11-19-07)
46
SMSC USB2513
DATASHEET
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
Chapter 7 Package Outlines
SMSC USB2513
Figure 7.1 36-Pin QFN, 6x6mm Body, 0.5mm Pitch
47 DATASHEET
Revision 1.98 (11-19-07)
USB 2.0 High-Speed 3-Port Hub Controller Datasheet
SMSC USB2513
Figure 7.2 48-Pin QFN, 7x7mm Body, 0.5mm Pitch
48 DATASHEET Revision 1.98 (11-19-07)

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